What was announced
On 3 August 2026, OLIX announced a $312M Series B at a $3.3bn post-money valuation. The euro figures reported alongside it are roughly €270.5M at a €2.8bn valuation; UK coverage put the valuation at more than £2bn.
| Item | Detail |
|---|---|
| Amount | $312M Series B |
| Valuation | $3.3bn post-money |
| Lead | Fundomo (New York) |
| Participating | Arm, Hudson River Trading, UK government Sovereign AI venture fund, existing investors increasing |
| Angel | Reed Hastings, Netflix co-founder |
| Founded | London, 2024 |
| Board addition | Professor Nick McKeown, Stanford emeritus and 2025 Marconi Prize winner |
| First customer delivery | Second half of 2027 |
The characterisation of this as Europe's largest-ever semiconductor funding round comes from the company and its coverage rather than an independent register, so treat the superlative as a claim rather than an audited fact. The underlying numbers are consistently reported across UK, EU and US outlets, and the presence of a government fund on the cap table is confirmed in multiple accounts.
The technical bet, stated plainly
OLIX is building rack-scale inference systems that combine custom silicon, photonics and networking. The first processor for its X-1 platform is the DX-1, a decode accelerator. It stores models in fast on-chip SRAM rather than depending on high-bandwidth memory.
That sentence contains two design decisions, and both are worth unpacking because they explain what the company is actually claiming.
Decode, not prefill
Inference splits into two phases with completely different hardware profiles. Prefill processes your prompt: it is compute-bound, highly parallel, and GPUs are excellent at it. Decode generates output tokens one at a time, and every single token requires reading the model's weights again. That makes decode memory-bandwidth bound — the arithmetic units sit idle waiting for weights to arrive.
Building a chip for decode alone is a legitimate specialisation, and it is the same logic that pushed Etched toward a transformer-only ASIC. The narrower your target, the more of the die you can dedicate to the thing that is actually the bottleneck. The risk is equally obvious: you have bet on the shape of today's workload persisting until your silicon ships.
SRAM instead of HBM
On-chip SRAM has dramatically higher bandwidth than off-chip HBM because the data never leaves the die. If decode is bandwidth-bound, that is the right lever to pull. It also sidesteps two supply constraints simultaneously — HBM availability and advanced packaging capacity — which have been genuine bottlenecks for everyone building accelerators.
The trade-off is capacity, and it is not a small one. SRAM is expensive per byte and there is not much of it on any die. A frontier-scale model does not fit on one chip, so an SRAM-first design has to shard weights across many chips and move activations between them at speed. That is precisely why the announcement talks about photonics and networking as part of the same system rather than as accessories: the interconnect becomes the new bottleneck the moment you solve the memory one.
No independent benchmarks exist. There is no published tokens-per-second figure, no cost-per-million-tokens, no power envelope, and no third party has run a model on this hardware. A $3.3bn valuation is a statement about investor conviction, not about silicon performance. Treat every architectural claim in this article as design intent — including the ones that sound most compelling.
Where this sits in a crowded field
Betting against the general-purpose GPU is currently one of the most well-funded ideas in technology, and it is worth seeing OLIX in that context rather than in isolation.
| Approach | Example | Core bet |
|---|---|---|
| Transformer-only ASIC | Etched | The architecture is stable enough to bake into silicon |
| Decode-specialised, SRAM-first | OLIX | Decode bandwidth is the binding constraint, and SRAM beats HBM for it |
| Hyperscaler in-house silicon | Google TPU, Amazon Trainium | Vertical integration beats margin-stacked purchasing |
| Software portability layer | Modular, acquired by Qualcomm | The moat is CUDA, so break the moat rather than the chip |
These are not mutually exclusive and the field is moving quickly — Anthropic has confirmed it is standing up its own chip team, and Qualcomm's $3.9B acquisition of Modular was explicitly a bet on the software side of the same problem. The reason so much capital is chasing this is straightforward: inference is where the recurring cost lives, and as we covered in our piece on rising GPU lease prices against falling model prices, the margin squeeze on anyone reselling inference is real and getting worse.
The UK sovereign angle
The UK government's Sovereign AI venture fund participating in this round is not incidental. Britain's AI industrial strategy has been criticised — fairly — for funding applications while the compute underneath them was imported. A domestic company designing inference silicon is the closest thing to an answer that policy has produced, and it lands the same week that the country's flagship research lab moved its operational reporting line to the United States.
It is also worth being honest about the limits. This is one company, at pre-revenue stage, with first delivery in late 2027, in a market where the incumbents ship at enormous scale today. Government participation in a Series B is a signal of intent, not a capability. The same fund's earlier deployments, which we covered when the £500M Sovereign AI Fund made its first investments, follow a similar pattern of early positions in long-horizon bets.
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Nothing changes in your 2026 or 2027 planning
Say this clearly because funding announcements have a way of leaking into roadmaps. Hardware that reaches initial customers in H2 2027 is not available to you in any meaningful sense until 2028, and that assumes no slip — which would make it the first accelerator programme in history not to slip. Your inference cost model should continue to assume GPUs and the pricing dynamics we set out in our guide to LLM unit economics and cost per task.
The prefill/decode split is worth internalising regardless
You do not need OLIX's silicon to benefit from understanding this. The distinction explains why batching helps decode enormously and prefill much less; why your tokens-per-second collapses at long context but your prompt processing does not; and why disaggregated serving — running prefill and decode on separate pools — is becoming standard practice in serving stacks. If the phrase "decode is bandwidth-bound" is new to you, that is a more useful takeaway from this announcement than the valuation is.
Measure the split in your own workload before you optimise anything. For a retrieval-augmented application with long contexts and short answers, prefill can dominate cost while decode dominates perceived latency. For a chat product, the reverse. Log input and output token counts per request for a week, and you will know which half of the problem you actually have — which also tells you whether prompt caching or batching is the higher-leverage fix.
The hiring is the near-term opportunity
A company at this valuation with silicon 18 months out needs a compiler and kernel team, a systems team, and — critically — an evaluation and modelling team that can prove the design works before there is hardware to run it on. Those roles open now, not in 2027.
That last category is worth flagging for anyone who thinks hardware companies only hire hardware people. Simulating workloads, building performance models, and constructing the benchmark suite that a chip is designed against is software work, and it is exactly the skill set that AI infrastructure engineers already have. It is also work that can be done remotely, which puts it within reach of engineers in Bengaluru or Chennai as much as Cambridge or London.
The short version
OLIX raised $312M at $3.3bn on 3 August 2026, led by Fundomo, with Arm, Hudson River Trading and the UK Sovereign AI fund participating, two years after being founded in London. The DX-1 is a decode-specialised accelerator that holds weights in on-chip SRAM rather than HBM, avoiding two live supply bottlenecks and creating a new interconnect problem that photonics is meant to solve. First customer delivery is H2 2027 and no independent performance data exists. Change nothing in your capacity planning. Do learn the prefill/decode distinction, and do watch the hiring — that part is happening now.
The company's own announcement is at olix.com, with independent coverage from Data Center Dynamics.